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2.5/3.3V 1:22 HIGH-PERFORMANCE, ClockWorksTM LOW-VOLTAGE PECL BUS CLOCK DRIVER SY89825U & TRANSLATOR w/ INTERNAL TERMINATION FINAL
FEATURES
s LVPECL or LVDS input to 22 LVPECL outputs s 100K ECL compatible outputs s LVDS input includes 100 termination s Guaranteed AC parameters over voltage:
DESCRIPTION
The SY89825U is a High Performance Bus Clock Driver with 22 differential LVPECL output pairs. This part is designed for use in low voltage (2.5V, 3.3V) applications which require a large number of outputs to drive precisely aligned, ultra low skew signals to their destination. The input is multiplexed from either LVDS or LVPECL by the CLK_SEL pin. The LVDS input includes a 100 internal termination, thus eliminating the need for external termination. The Output Enable (OE) is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state. This eliminates any chance of generating a runt clock pulse when the device is enabled/ disabled as can happen with an asynchronous control. The SY89825U features low pin-to-pin skew (35ps max.) --performance previously unachievable in a standard product having such a high number of outputs. The SY89825U is available in a single space saving package which provides a lower overall cost solution. In addition, a single chip solution improves timing budgets by eliminating the multiple device solution with their corresponding large part-to-part skew.
s s s s
* > 2GHz fMAX (toggle) * < 35ps max. ch-ch skew Low voltage operation: 2.5V, 3.3V Temperature range: -40C to +85C Output enable pin Available in a 64-Pin EPAD-TQFP
PIN CONFIGURATION
VCCO /Q6 Q6 /Q5 Q5 /Q4 Q4 /Q3 Q3 /Q2 Q2 /Q1 Q1 /Q0 Q0 VCCO
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 VCCO NC NC VCCI LVDS_CLK /LVDS_CLK CLK_SEL LVPECL_CLK /LVPECL_CLK GND OE NC NC /Q21 Q21 VCCO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VCCO Q7 /Q7 Q8 /Q8 Q9 /Q9 Q10 /Q10 Q11 /Q11 Q12 /Q12 Q13 /Q13 VCCO
APPLICATIONS
s High-performance PCs s Workstations s Parallel processor-based systems s Other high-performance computing s Communications
64-Pin EPAD-TQFP (Top View)
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
VCCO /Q20 Q20 /Q19 Q19 /Q18 Q18 /Q17 Q17 /Q16 Q16 /Q15 Q15 /Q14 Q14 VCCO
Rev.: A
Amendment: /0
1
Issue Date: September 2001
Micrel
ClockWorksTM SY89825U
PIN NAMES
Pin LVDS_CLK, /LVDS_CLK LVPECL_CLK, /LVPECL_CLK CLK_SEL OE Q0 - Q21, /Q0 - /Q21 GND VCCI Function Differential LVDS Inputs (Internal 100 termination included) Differential LVPECL Inputs. Input CLK Select (LVTTL) Output Enable (LVTTL) Differential LVPECL Outputs. Terminate with 50 to VCC-2V Ground Power Supply. Connect to VCC on PCB. VCCI and VCCO are not internally connected Power Supply for Output Buffer. Connect to VCCI on PCB. VCCI and VCCO are not internally connected
LOGIC SYMBOL
CLK_SEL LVDS_CLK /LVDS_CLK
0 22 22 Q0 - Q21 /Q0 - /Q21
LVPECL_CLK
1
/LVPECL_CLK LEN Q OE D
VCCO
TRUTH TABLE
OE(1) 0 0 1 1 CLK_SEL 0 1 0 1 Q0 - Q21 LOW LOW LVDS_CLK LVPECL_CLK /Q0 - /Q21 HIGH HIGH /LVDS_CLK /LVPECL_CLK
SIGNAL GROUPS
Signal LVDS_CLK, /LVDS_CLK Q0 - Q21, /Q0 - /Q21 LVPECL_CLK, /LVPECL_CLK CLK_SEL, OE I/O Input Output Input Input LVDS LVPECL LVPECL LVCMOS/LVTTL Level
NOTE: 1. The OE (output enable) signal is synchronized with the low level of the LVDS_CLK and LVPECL_CLK signal.
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VCCI / VCCO VIN IOUT Tstore JA Rating VCC Pin Potential to Ground Pin Input Voltage DC Output Current Storage Temperature Package Thermal Resistance (Junction-to-Ambient) With exposed pad soldered to GND - Still-Air (multi-layer PCB) - 200lfpm (multi-layer PCB) - 500lfpm (multi-layer PCB) Exposed pad not soldered to GND - Still-Air (multi-layer PCB) - 200lfpm (multi-layer PCB) - 500lfpm (multi-layer PCB) Value -0.5 to +4.0 -0.5 to VCCI -50 -65 to +150 23 18 15 44 36 30 4.3 Unit V V mA C C/W C/W C/W C/W C/W C/W C/W
JC
Package Thermal Resistance (Junction-to-Case)
NOTE: 1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data book. Exposure to ABSOLUTE MAXIMUM RATING conditions for extended periods may affect device reliability.
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ClockWorksTM SY89825U
DC ELECTRICAL CHARACTERISTICS
Power Supply
TA = -40C Symbol VCCI, VCCO ICC Power Parameter Supply(1) Min. 2.37 -- Typ. -- 100 Max. 3.6 150 Min. 2.37 -- TA = +25C Typ. -- 100 Max. 3.8 150 Min. 2.37 -- TA = +85C Typ. -- 100 Max. 3.6 150 Unit V mA
Total Supply Current(2)
NOTES: 1. VCCI and VCCO must be connected together on the PCB such that they remain at the same potential. VCCI and VCCO are not internally connected on the die. 2. No load. Outputs floating.
LVDS Input (VCC = 2.37V to 3.6V, GND = 0V)
TA = -40C Symbol VIN VID IIL RIN Parameter Input Voltage Range Differential Input Swing Input Low Current(1) LVDS Differential Input Resistance (LVDS_CLK to /LVDS_CLK) Min. 0 100 -1.25 80 Typ. -- -- -- 100 Max. 2.4 -- -- 120 Min. 0 100 -1.25 80 TA = +25C Typ. -- -- -- 100 Max. 2.4 -- -- 120 Min. 0 100 -1.25 80 TA = +85C Typ. -- -- -- 100 Max. 2.4 -- -- 120 Unit V mV mA
NOTE: 1. For IIL, both LVDS inputs are grounded.
LVPECL Input/Output (VCC = 2.37V to 3.6V, GND = 0V)
TA = -40C Symbol VIH VIL VPP VCMR VOH VOL IIH IIL Parameter Input HIGH Voltage (Single ended) Input LOW Voltage Minimum Input LVPECL_CLK Swing(1) Min. VCC - 1.165 VCC - 1.945 600 -1.5 Max. VCC - 0.88 TA = +25C Min. VCC - 1.165 Max. VCC - 0.88 VCC - 1.625 -- -0.4 TA = +85C Min. VCC - 1.165 VCC - 1.945 600 -1.5 Max. VCC - 0.88 VCC - 1.625 -- -0.4 Unit V V mV V V V A A
VCC - 1.625 VCC - 1.945 -- -0.4 600 -1.5
Common Mode Range(2) LVPECL_CLK Output HIGH Voltage(3) Output LOW Voltage(3) Input HIGH Current Input LOW Current
VCCO - 1.085 VCCO - 0.880 VCCO - 1.025 VCCO - 0.880 VCCO - 1.025 VCCO - 0.880 VCCO - 1.830 VCCO - 1.555 VCCO - 1.810 VCCO - 1.620 VCCO - 1.810 VCCO - 1.620 -- 0.5 150 -- -- 0.5 150 -- -- 0.5 150 --
NOTES: 1. The VPP (min.) is defined as the minimum input differential voltage which will cause no increase in the propagation delay. 2. VCMR is defined as the range within which the VIH level may vary, with the device still meeting the propagation delay specification. The numbers in the table are referenced to VCCI. The VIL level must be such that the peak-to-peak voltage is less than 1.0V and greater than or equal to VPP (min.). The lower end of the CMR range varies 1:1 with VCCI. The VCMR (min) will be fixed at 3.3V - |VCMR (min)|. 3. Outputs loaded with 50 to VCC -2V.
LVCMOS/LVTTL Control Inputs (OE, CLK_SEL) (VCC = 2.37V to 3.6V, GND = 0V)
TA = -40C Symbol VIH VIL IIH IIL Parameter Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current Min. 2.0 -- +20 -- Typ. -- -- -- -- Max. -- 0.8 -250 -600 3 Min. 2.0 -- +20 -- TA = +25C Typ. -- -- -- -- Max. -- 0.8 -250 -600 Min. 2.0 -- +20 -- TA = +85C Typ. -- -- -- -- Max. -- 0.8 -250 -600 Unit V V A A
Micrel
ClockWorksTM SY89825U
AC ELECTRICAL CHARACTERISTICS(1)
VCC = 2.37V to 3.6V, GND = 0V
TA = -40C Symbol fMAX tPHL tPLH tSKEW tS(OE) tH(OE) tr tf Parameter Max Toggle Frequency(2) Propagation Delay (Differential)(3) LVPECL IN LVDS IN Within-Device Skew(4) Part-to-Part Skew(5) OE Set-Up Time(6) OE Hold Time(6) Output Rise/Fall Time (20% - 80%) Min. 2 0.600 0.800 -- -- 1.0 0.5 300 -- Typ. -- -- -- -- 100 -- -- -- -- Max. -- 1.2 1.4 35 200 -- -- 600 1.2 Min. 2 0.600 0.800 -- -- 1.0 0.5 300 -- TA = +25C Typ. -- 0.900 1.1 20 100 -- -- 450 -- Max. -- 1.2 1.4 35 200 -- -- 600 1.2 2 0.600 0.800 -- -- 1.0 0.5 300 -- TA = +85C Min. Typ. -- -- -- -- 100 -- -- -- -- Max. -- 1.2 1.4 35 200 -- -- 600 1.2 ps ps ns ns ps ns Unit GHz ns
t(switchover) Input Switchover CLK_SEL-to-valid output
NOTES: 1. Outputs loaded with 50 to VCC - 2V. Airflow 300lfpm. 2. fMAX is defined as the maximum toggle frequency measured. Measured with a 750mV input signal, all loading with 50 to VCC -2V. 3. Differential propagation delay is defined as the delay from the crossing point of the differential input signals to the crossing point of the differential output signals. 4. The within-device skew is defined as the worst case difference between any two similar delay paths within a single device operating at the same voltage and temperature. 5. The part-to-part skew is defined as the absolute worst case difference between any two delay paths on any two devices operating at the same voltage and temperature. Part-to-part skew is the total skew difference; pin-to-pin skew + part-to-part skew. 6. Set-up and hold time applies to synchronous applications that intend to enable/disable before the next clock cycle. For asynchronous applications, set-up and hold time does not apply. OE set-up time is defined with respect to the rising edge of the clock. OE HIGH to LOW transition ensures outputs remain disabled during the next clock cycle. OE LOW to HIGH transition enables normal operation of the next input clock.
PRODUCT ORDERING CODE
Ordering Code SY89825UHI Package Type H64-1 Operating Range Industrial Package Marking SY89825UHI
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ClockWorksTM SY89825U
LVDS/LVPECL INPUTS
VCC
VCC
1.9k
1.9k
75k LVPECL_CLK 75k 75k
VIN 100
1.9k
1.9k
/LVPECL_CLK
VIN
GND
GND
LVPECL Input Stage Figure 1. Simplified LVPECL & LVDS Input Stage
LVDS Input Stage
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ClockWorksTM SY89825U
TYPICAL CHARACTERISTICS
Frequency Response vs. Output Amplitude
900 900
Frequency Response vs. Output Amplitude
OUTPUT AMPLITUDE (mV)
800 700 600 500 400 300 200 VSUP = 3.3V VDIFFIN = 800mV
OUTPUT AMPLITUDE (mV)
800 700 600 500 400 300 200
VSUP = 2.5V VDIFFIN = 800mV
0
1000
1500
2000
2500
3000
3500
4000
0
1000
1500
2000
2500
3000
3500
FREQUENCY (MHz)
FREQUENCY (MHz)
Frequency Response vs. Output Amplitude @2.5V
Frequency Response vs. Output Amplitude @3.3V
6
4000
500
500
100
100
Micrel
ClockWorksTM SY89825U
LVPECL TERMINATION RECOMMENDATIONS
Output Considerations Be sure to properly terminate all outputs as shown below, or equivalent. For AC coupled applications, be sure to include a pull
down resistor at the output of each driver. The emmiter follower outputs requires a DC current path to GND. Unused outputs can be left floating with minimal impact on skew and jitter.
+3.3V
+3.3V
R1 130 ZO = 50
R1 130
+3.3V
ZO = 50 R2 82 R2 82 Vt = VCC --2V
Figure 1. Parallel Termination-Thevenin Equivalent Notes: 1. For +2.5V systems: R1 = 250 R2 = 62.5
+3.3V "source"
Z = 50
+3.3V "destination"
Z = 50 50 50
46 to 49
Rb
Figure 2. Three-Resistor "Y-Termination" Notes: 1. Power-saving alternative to Thevenin termination. 2. Place termination resistors as close to destination inputs as possible. 3. Rb resistor sets the DC bias voltage equal to Vt. For +3.3V systems Rb = 46 to 49. 4. Precision, low-cost 3-Resistor networks are available from resistor manufacturers such as Thin Film Technology (www.thinfilm.com).
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Micrel
ClockWorksTM SY89825U
64 LEAD EPAD-TQFP (DIE UP) (H64-1)
12.00 0.472 BSC SQ. 4 10.00 0.394 BSC SQ. 4.50 0.177
64
+0.05 -0.05 +0.012 -0.012
1.00 +0.05 -0.05 0.039 +0.002 -0.002
DETAIL "A"
0 MIN.
67 0.20 0.008 0.09 0.004
48
6
0.15 0.006 0.05 0.002
48
0- 7 4.50 +0.03 -0.03 0.177+0.012 -0.012 0.60 +0.15 -0.15 0.024 +0.006 -0.006 1.00 0.039 REF.
33
16
17
32
5 1.20 0.047 MAX 0.50 0.020
BSC SEE DETAIL "A"
0.01 0.004
7 0.22 +0.05 -0.05 0.009 +0.002 -0.002
Rev. 03
MICREL-SYNERGY 3250 SCOTT BOULEVARD
TEL
SANTA CLARA CA 95054
WEB
USA
+ 1 (408) 980-9191
FAX
+ 1 (408) 914-7878
http://www.micrel.com
This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. (c) 2001 Micrel Incorporated
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